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A1222+ memory interleaving
Not too shy to talk
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Please,

do somebody know, if A1222+ can use memory bank interleaving?

I am using 8 GB memory with 2 ranks - i.e 2Rx8. All 8 GB are recognized. U-Boot:
DDR:399.960 MHz (799.920 MT/s data rate) (Asynchronous), LBC:49.995 MHz
....
DRAM:  Detected UDIMM KF1866C11S3L/8G
8 GiB 
(DDR364-bitCL=6ECC off)

So according the P1022 reference manual it has Chip select interleaving support. But I am not sure, if chip select signal can select different ranks in one physical module.

I also not found any suitable U-Boot command to check this ( like dramcfg on X1000 ).
And if I compare Ragemem speed, it is the same like eliyahu has in his great article. And his memory is 1Rx16.

Do you have any idea how to test it?
Or do somebody know well memory topology - is memory interleaving possible with this motherboard configuration? ( only one module )

Thank for ideas.

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor

Yes, that is the whole idea behind rank interleaving. Each rank has its own chip select.

See my explaination here: https://www.amigans.net/modules/newbb/ ... id=128527#forumpost128527

By saving activation and precharge commands, you'll reduce overall latency and therefore gain about 10% speed.

If supported by the P1022 the it still needs to be activated in uboot. The X5000 has a environmental variable for that which is set to rank interleaving (and controller interleaving) by default.

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Re: A1222+ memory interleaving
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@geennaam

It looks like this is the line you are thinking of on the X5000:

hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host,phy_type=utmi

Here is the hwconfig on the A1222:

hwconfig=esdhc;audclk:12;usb1:dr_mode=host,phy_type=ulpi

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Re: A1222+ memory interleaving
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From P1022 manual:
DDR SDRAM control configuration register

bit 17–23 BA_INTLV_CTL
:

xx 00100 External memory banks 0 through 3 are all interleaved together
0000000 No external memory banks are interleaved
1000000 External memory banks 0 
and 1 are interleaved
0100000 External memory banks 2 
and 3 are interleaved
1100000 External memory banks 0 
and 1 are interleaved together and banks 2 and 3 are interleaved together

If I assume, that used ranks are bank 0 and bank 1,
I would test to add bank_intlv=cs0_cs1 to hwconfig, but it still depends if A1222+ U-Boot has this parameter in this exact form.

Do somebody have U-Boot manual or more deeper information?

@geennaam - I read your great explanation, and that is why I am checking this on P1022. Thx!

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor

It's a uboot env. Not specific to the X5000. The question is if the variable is just ignored or actually implemented for the P1022.

If you want to be on the safe side then you can clone your sdcard first with eg. win32diskimager. And then try adding the following to hwconfig env: fsl_ddr:bank_intlv=cs0_cs1 and see what happens.

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Re: A1222+ memory interleaving
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@geennaam
good idea. I cloned my SDcard already, but only to NGFS disk on A1222+, which shouln't be enough for A1222+ recovery

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor
Quote:
Do somebody have U-Boot manual or more deeper information?


Fortunately U-Boot is GPL so if all else fails one can check the source to know exactly what is it doing and what is supported or not. That's probably better than any documentation.

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Re: A1222+ memory interleaving
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@balaton

Yes, however, I don't think the A1222 changes are available anywhere. Not sure if Trevor owns it or Matthew or both (as A-EON).

-- eliyahu

"Physical reality is consistent with universal laws. When the laws do not operate, there is no reality. All of this is unreal."
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Re: A1222+ memory interleaving
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And simpliest way how to clone card shuld be do it on A1222+ directly with SDclone.

Is it possible ( and safe ) to remove microSD with U-Boot from running system?

It should be, because AmigaOS not use the SD, but want to be sure. Not want to destroy my only B-Boot

Edit: I found external USB SDC reader, and successfuly made backup with A1222+.


Edited by sailor on 2024/3/22 18:10:21
AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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Just tested interleaving with:
hwconfig=esdhc;fsl_ddr:bank_intlv=cs0_cs1;audclk:12;usb1:dr_mode=host,phy_type=ulpi

the good thing: A1222+ not bricked
the bad thing: interleaving not working - both output from UBoot and ragemem speed are the same

@balaton
please, do you have any idea what u-boot repo is closest to our A1222+? There are hundreds of them on git.

@all
please, are there any way how ask A1222+ U-boot developers?

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor
Quote:
@balaton
please, do you have any idea what u-boot repo is closest to our A1222+? There are hundreds of them on git.

No idea, probably none of them.
Quote:
@all
please, are there any way how ask A1222+ U-boot developers?

The GPL says that whoever distributes binaries of GPL code should also accompany it with the source or at least an address where you can get the source. So contact whover sent you the board that contains the U-Boot binary and they should sort it out otherwise they would illegally distribute binaries they are not allowed to so they should stop doing that and play by the rules.

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Re: A1222+ memory interleaving
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@sailor

Uboot is open source and you can request a copy from the ExecSG team. I would try Steven Solie.
amigaboot is owned by Trevor and is closed source.

Maybe the A1222+ has it's DDR on chip selects two and three.

You can try fsl_ddr:bank_intlv=cs2_cs3

Or maybe fsl_ddr:bank_intlv=auto works for you.

If they are on 0,2 1,3 or 0,3 then it is game over.

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Re: A1222+ memory interleaving
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@geennaam
thank you, it will ne nice!

Just now I tested both fsl_ddr:bank_intlv=cs2_cs3 and fsl_ddr:bank_intlv=auto, with the same result - speed is the same like eliyahu`s 1R memory.

Also can be, that option in A1222 U-Boot missing.

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor

Can you give a bit more output? Is it using the SPD for configuration?

DRAM:  Initializing....using SPD

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Re: A1222+ memory interleaving
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This line missing in A1222+ log:

U-Boot aeon-2024-02-02 (Feb 02 2024 02:00:39)

CPU0:  P1022Version1.1, (0x80e60011)
Core:  e500Version5.1, (0x80211151)
Clock Configuration:
       
CPU0:1199.880 MHzCPU1:1199.880 MHz,
       
CCB:399.960 MHz,
       
DDR:399.960 MHz (799.920 MT/s data rate) (Asynchronous), LBC:49.995 MHz
L1
:    D-cache 32 KiB enabled
       I
-cache 32 KiB enabled
Board
Tabor
I2C
:   ready
SPI
:   ready
DRAM
:  Detected UDIMM KF1866C11S3L/8G
8 GiB 
(DDR364-bitCL=6ECC off)
L2:    256 KiB already enabled
MMC
:  FSL_SDHC0
MAC
80:34:28:6F:8F:B9
MAC
FC:0F:E7:0F:C7:BB
EEPROM
Invalid ID (ff ff ff ff)
PCIe1Root Complex of Slot 1x4 gen1regs 0xffe0a000
  01
:00.0     1002:67df Display controller
  01
:00.1     1002:aaf0 Multimedia device
PCIe1
Bus 00 01
Pins 
0x0
Looking 
for VGA
videoboot
Booting PCI video card bus 1, function 0device 0
Begin BIOS POST
End BIOS POST
Setting VESA Mode
Found required VESA mode
About to set mode 279
About to get mode
Got mode 49431 
(0xc117)
OK
XSize 
1024 YSize 768 Base =0xe0000000
mmio_base 
0xc0000000
bgx 
0xad55ad55 fgx 0x0
In
:    serial
Out
:   serial
Err
:   serial
SCSI
:  scanning bus for devices...
Found 0 device(s).
Net:   Tuning PHY 3
Tuning PHY 
7
eTSEC1
eTSEC2
USB0
:   USB EHCI 1.00
scanning bus 0 
for devices... 4 USB Device(sfound
SATA0 
(3 Gbps)
       
SATA1 (1.5 Gbps)
CE at device
scanning bus 
for devices...
No medium present
  Device 0
: (1:0VendorHL-DT-ST Prod.: DVDRAM GTC2N Rev1.00
            Type
Removable CD ROM
            Capacity
not available
Found 1 device
(s).
## Starting application at 0x00200000 ...


P.S: this log is without any fsl_ddr: parameter. But with it logs not differs.

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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@sailor

Ok forget that SPD line, it is only printed for the X5000.

I don't see any particular restriction in u-boot why the Tabor would not support interleaving.

Tabor is configured for 1 DIMM with 2 chip selects.

It should be using SPD info

It should activate bank interleaving when the env is set properly and have found dual rank memory.

The line "DDR Chip-Select Interleaving Mode: CS0+CS1" Should be printed when it is activated.

But since the line isn't printed it clearly isn't activated for you.

It takes a deep dive to find the root cause why bank interleaving is not enabled. Which is a bit too much effort for me at the moment.

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Re: A1222+ memory interleaving
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@geennaam
thanks for support!

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: A1222+ memory interleaving
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I have some experience with DRAM on the A1222.
I can offer a few details, and a path to get more.

I've been absent, and I only came here today because a friend suggested I check this topic out. I'm not "gone forever", but a new job, a move to a new state, and WAY too many personal obligations have effectively eliminated Amiga time for me, for a while anyway.

Fair Warning: There are some "adjustments" that have been made to get P1022 RAM to accommodate AmigaOS. Just because "UBOOT" , or just because "Linux" DOES NOT MEAN that AmigaOS on the same board will offer the same features. That's as deep as I'll go on that.

I HAVE looked at a LOT of RAM SPD data on the A1222, and I recall at least one stick that looked like two sticks according to SPD. I tested a LOT of ram, some worked, some did not. Too long of a story to tell.

I have written two rather crude tools for SPD.
One gathers the SPD data and outputs a data file, the second reads that data and does SOME (not all) decoding and translation.
These tools are offered freely to anyone who wants them.
Since they were written for A1222, they only look at the first stick of RAM, but anyone with a bit of play time could expand them to see additional sticks on a X5000 easily enough.


I don't have a website. I'll find the tools and forward it to anyone who asks me, be patient as it might take a day or two.
Anyone whom gets these tools is free to re-distribute however they see fit.

No warranty is expressed or implied, use at your own risk.. all the usual.

lylehaze at gmail dot com.

All I missed is "What is SPD"??
RAM sticks carry a small ROM that describes their size, speeds, and capabilities. The computer reads that and then adjust the hardware to make best use of the RAM abilities. There are various versions, revisions and formats. You can read SPD directly from a UBOOT command line, but it's not graceful.

Those asking for these tools will probably just get a forwarded email, as I don't currently have an A1222 to boot up.

Have Fun,
lylehaze

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Re: A1222+ memory interleaving
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@LyleHaze

Hi!

I will send you an mail and ask for the tools.
But IMHO tools like this doesn't deserve to be buried in a forum post even if the output probably is only readable for people with insight, they should be available online on os4depot or similar :)

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Re: A1222+ memory interleaving
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@smf
Maybe you can ask permission to put them on os4depot, included sources for further development.

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