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X1000 and interleaved memory controllers
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Hello guys,
I used the stream_memspeed program (available on OS4Depot) to measure memory speed with the following two configurations:

1) 2GB module fitted to DIMM1
2) 2GB module fitted to DIMM1 & 2GB module fitted to DIMM3

However the second configuration should use interlaced controllers, so I would have expected a doubling of the memory bandwidth,according to the X1000 documentation (First_contact_Nemo_v1.5.pdf).
Instead I get pretty much the same speed, according to the results of stream_memspeed.

Am I doing something wrong?


Note: AmigaOS4.1, due to the 2GB limit, only sees 2GB even in the second configuration where 4GB of RAM is mounted.

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Re: X1000 and interleaved memory controllers
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@AlfredOne

At first you have to be sure you use modules with exactly the same geometry ( size, speed, latency, rows...). The best way is to buy 2x2GB kit for dual channel. If you have different geometry, interleaving / dual channel not works.

If you use equal RAM modules, and still there is no speed increase, try to test speed with linux. For example Fienix is very easy to install on X1000 ( https://forum.hyperion-entertainment.com/viewtopic.php?f=35&t=4908 )

You can also try modules in DIMM2 and DIMM4 slots

And you can look on CFE, if there is some clue ( for example show dramcfg or similar command or serial debug ).

I can check it with my X1000, but not now - I have many unfinished project with other AmigaNG
But I have to say, that memory controller of PA-Semi CPU is not ideal - for example I cannot found any combination with all 4 modules.

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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@AlfredOne

Save some time maybe, since CFE/hardware is still on the same version

https://www.amigans.net/modules/newbb/ ... id=114969#forumpost114969

Quote:

I played around with memory sticks and found that my (probably all) hardware seems to be defect when it comes to bank interleaving.

Either that or CFE was never tested with either more than 4 GB in place or all banks populated with modules.

Under WB only 2 GB are visible, i know that, but having (perfectly fine and usable) 4x 4 GB sticks in all the banks, i get sudden hardware(!) shutdowns as soon as i let ragemem run under WB.
It always breaks when it starts testing the L2 cache.

Other programs display that behaviour too, memory hungry stuff, like ScummVM and ResidualVM.

This is with 16 GB and 8 GB in place on interleaved banks (i.e. bank 1 and 3, bank 2 and 4).

2x 16 GB on different banks i can't test due to lack of modules, but 2x 4 GB works perfectly fine under WB (if on different banks), no more sudden shutdown, nothing, stable as a rock, as soon as i plug the other two 4 GB modules in (same developer, same brand, same module) OR i set two of those modules on interleave,i get the dropouts

People are dying.
Entire ecosystems are collapsing.
We are in the beginning of a mass extinction.
And all you can talk about is money and fairytales of eternal economic growth.
How dare you!
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Re: X1000 and interleaved memory controllers
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@sailor

This is the dramcfg output:

CFE> show dramcfg␍␊
[12:37:25:425] SDRAM: ECC off, Non-ECC DIMM used on channel 0.␍␊
[12:37:25:429] SDRAM: ECC off, Non-ECC DIMM used on channel 1.␍␊
[12:37:25:462] DRAM runtime configuration:␍␊
[12:37:25:462] Total memory: 4096MB␍␊
[12:37:25:462] Channel interleaved ␍␊
[12:37:25:462] XAUI␍␊
[12:37:25:462] ␍␊
[12:37:25:462] Channel 0:␍␊
[12:37:25:462] 2048MB of RAM, Address Range 0 - 6144MB␍␊
[12:37:25:462] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[12:37:25:462] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[12:37:25:462] High performance mode␍␊
[12:37:25:462] MMC advanced features␍␊
[12:37:25:462] DRAM Rtt: 150 Ohms␍␊
[12:37:25:462] MMC Rtt0: 75 Ohms␍␊
[12:37:25:462] MMC Rtt1: 75 Ohms␍␊
[12:37:25:508] MC & DRAM ODT␍␊
[12:37:25:508] Addr/Cmd 2T Timing␍␊
[12:37:25:508] Ctrl Output Phase wrt CLK: 0␍␊
[12:37:25:508] Addr/Cmd Output Phase wrt CLK: 0␍␊
[12:37:25:508] Rank interleaved␍␊
[12:37:25:508] UDIMM␍␊
[12:37:25:508] ␍␊
[12:37:25:508] Channel 1:␍␊
[12:37:25:508] 2048MB of RAM, Address Range 0 - 6144MB␍␊
[12:37:25:508] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[12:37:25:508] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[12:37:25:508] High performance mode␍␊
[12:37:25:508] MMC advanced features␍␊
[12:37:25:508] DRAM Rtt: 150 Ohms␍␊
[12:37:25:508] MMC Rtt0: 75 Ohms␍␊
[12:37:25:508] MMC Rtt1: 75 Ohms␍␊
[12:37:25:508] MC & DRAM ODT␍␊
[12:37:25:508] Addr/Cmd 2T Timing␍␊
[12:37:25:508] Ctrl Output Phase wrt CLK: 0␍␊
[12:37:25:508] Addr/Cmd Output Phase wrt CLK: 0␍␊
[12:37:25:508] Rank interleaved␍␊
[12:37:25:508] UDIMM␍␊

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Re: X1000 and interleaved memory controllers
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There were rumours about RAM: driver utilizing memory beyond 2 GB on AmigaOS 4 for RAM Disk: storage, hence the reason I still keep 8 GB in my X1000 since summer 2020. Now almost 4 years later, still no public available driver yet.

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Re: X1000 and interleaved memory controllers
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@drHirudo

Yes, i know that that currently I can only see 2GB even though I have 4GB = 2x2GB installed.

I wonder if the 2 GB visible are the result of 1GB + 1GB taken from two interlaced RAM modules or if they are taken entirely from just one of the two RAM modules.

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Re: X1000 and interleaved memory controllers
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@AlfredOne

Nope, the first 2 GB will be utilized, no matter if you have 2x2GB, 2x4GB or 4x4GB

2x2GB for example will never touch the second ram bank

Only when you use 2x1GB it will switch to interleave...but as i wrote above, expect a rocky road

People are dying.
Entire ecosystems are collapsing.
We are in the beginning of a mass extinction.
And all you can talk about is money and fairytales of eternal economic growth.
How dare you!
– Greta Thunberg
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Re: X1000 and interleaved memory controllers
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@drHirudoQuote:
drHirudo wrote:There were rumours about RAM: driver utilizing memory beyond 2 GB on AmigaOS 4 for RAM Disk: storage, hence the reason I still keep 8 GB in my X1000 since summer 2020. Now almost 4 years later, still no public available driver yet.


RAM above 2GB should be use like Extended memory: Breaking the Memory Barrier

It means, that program have to be coded with this feature. Like Rave for example.
Rave from Daniel Jedlička is only program I know that use this. Maybe there are some more...

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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@AlfredOne
your output states, that RAM module are interleaved.
So I have no other clue

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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@Raziel

CFE shows that 2x2GB are interleaved.

Shouldn't it be transparent at the OS level whether it's interleaved or not?

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Re: X1000 and interleaved memory controllers
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@AlfredOne

pls, read this: x5000 benchmarks / speed up

it looks like memory benchmarks are a little more complex

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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@AlfredOne

probably...but does cfe pass that information along?
i doubt it

People are dying.
Entire ecosystems are collapsing.
We are in the beginning of a mass extinction.
And all you can talk about is money and fairytales of eternal economic growth.
How dare you!
– Greta Thunberg
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Re: X1000 and interleaved memory controllers
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@Raziel

I believe there is no need for CFE to pass on this information.
AmigaOS4 doesn't have to know if the memory is interleaved or not.
It's the memory controllers that handle everything.

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Re: X1000 and interleaved memory controllers
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I tested the following 3 configurations:

1) 1x2GB DIMM on Slot1

CFE relevant output:
SDRAMECC offNon-ECC DIMM used on channel 0.␍␊
[09:30:40:111DRAM runtime configuration:␍␊
[09:30:40:130Total memory2048MB␍␊
[09:30:40:130XAUI␍␊
[09:30:40:130␍␊
[09:30:40:130Channel 0:␍␊
[09:30:40:1302048MB of RAMAddress Range 0 2048MB␍␊
[09:30:40:130Memory clock 400MHz (DDR2-800), tCK 2500psCL 6␍␊
[09:30:40:130Low Latency Config Tuned for Fcore 2000 MHz␍␊
[09:30:40:130High performance mode␍␊
[09:30:40:170MMC advanced features␍␊
[09:30:40:170DRAM Rtt150 Ohms␍␊
[09:30:40:170MMC Rtt075 Ohms␍␊
[09:30:40:170MMC Rtt175 Ohms␍␊
[09:30:40:170MC DRAM ODT␍␊
[09:30:40:170Addr/Cmd 2T Timing␍␊
[09:30:40:170Ctrl Output Phase wrt CLK0␍␊
[09:30:40:170Addr/Cmd Output Phase wrt CLK0␍␊
[09:30:40:170Rank interleaved␍␊
[09:30:40:170UDIMM



2) 2x2GB DIMM on Slot1 & Slot2

CFE relevant output:
[09:12:29:334SDRAMECC offNon-ECC DIMM used on channel 0.␍␊
[09:12:29:338DRAM runtime configuration:␍␊
[09:12:29:386Total memory4096MB␍␊
[09:12:29:386XAUI␍␊
[09:12:29:386␍␊
[09:12:29:386Channel 0:␍␊
[09:12:29:3864096MB of RAMAddress Range 0 6144MB␍␊
[09:12:29:386Memory clock 400MHz (DDR2-800), tCK 2500psCL 6␍␊
[09:12:29:386Low Latency Config Tuned for Fcore 2000 MHz␍␊
[09:12:29:386High performance mode␍␊
[09:12:29:386MMC advanced features␍␊
[09:12:29:386DRAM Rtt50 Ohms␍␊
[09:12:29:386MMC Rtt0150 Ohms␍␊
[09:12:29:386MMC Rtt1150 Ohms␍␊
[09:12:29:386MC DRAM ODT␍␊
[09:12:29:386Addr/Cmd 2T Timing␍␊
[09:12:29:386Ctrl Output Phase wrt CLK0␍␊
[09:12:29:386Addr/Cmd Output Phase wrt CLK0␍␊
[09:12:29:386Rank interleaved␍␊
[09:12:29:386UDIMM



3) 2x2GB DIMM on Slot1 & Slot3

CFE relevant output:
[09:43:48:319SDRAMECC offNon-ECC DIMM used on channel 0.␍␊
[09:43:48:327SDRAMECC offNon-ECC DIMM used on channel 1.␍␊
[09:43:48:363DRAM runtime configuration:␍␊
[09:43:48:363Total memory4096MB␍␊
[09:43:48:363Channel interleaved ␍␊
[09:43:48:363XAUI␍␊
[09:43:48:363␍␊
[09:43:48:363Channel 0:␍␊
[09:43:48:3632048MB of RAMAddress Range 0 6144MB␍␊
[09:43:48:363Memory clock 400MHz (DDR2-800), tCK 2500psCL 6␍␊
[09:43:48:363Low Latency Config Tuned for Fcore 2000 MHz␍␊
[09:43:48:363High performance mode␍␊
[09:43:48:363MMC advanced features␍␊
[09:43:48:363DRAM Rtt150 Ohms␍␊
[09:43:48:363MMC Rtt075 Ohms␍␊
[09:43:48:363MMC Rtt175 Ohms␍␊
[09:43:48:363MC DRAM ODT␍␊
[09:43:48:363Addr/Cmd 2T Timing␍␊
[09:43:48:363Ctrl Output Phase wrt CLK0␍␊
[09:43:48:363Addr/Cmd Output Phase wrt CLK0␍␊
[09:43:48:424Rank interleaved␍␊
[09:43:48:424UDIMM␍␊
[09:43:48:424␍␊
[09:43:48:424Channel 1:␍␊
[09:43:48:4242048MB of RAMAddress Range 0 6144MB␍␊
[09:43:48:424Memory clock 400MHz (DDR2-800), tCK 2500psCL 6␍␊
[09:43:48:424Low Latency Config Tuned for Fcore 2000 MHz␍␊
[09:43:48:424High performance mode␍␊
[09:43:48:424MMC advanced features␍␊
[09:43:48:424DRAM Rtt150 Ohms␍␊
[09:43:48:424MMC Rtt075 Ohms␍␊
[09:43:48:424MMC Rtt175 Ohms␍␊
[09:43:48:424MC DRAM ODT␍␊
[09:43:48:424Addr/Cmd 2T Timing␍␊
[09:43:48:424Ctrl Output Phase wrt CLK0␍␊
[09:43:48:424Addr/Cmd Output Phase wrt CLK0␍␊
[09:43:48:424Rank interleaved␍␊
[09:43:48:424UDIMM



RageMem results:

1)
---> RAM <---
READ32: 2822 MB/Sec
READ64: 4049 MB/Sec
WRITE32: 2374 MB/Sec
WRITE64: 2284 MB/Sec
WRITE: 340 MB/Sec (Tricky)

2)
---> RAM <---
READ32: 2837 MB/Sec
READ64: 4077 MB/Sec
WRITE32: 2387 MB/Sec
WRITE64: 2295 MB/Sec
WRITE: 339 MB/Sec (Tricky)

3)
---> RAM <---
READ32: 2827 MB/Sec
READ64: 3961 MB/Sec
WRITE32: 2725 MB/Sec
WRITE64: 3252 MB/Sec
WRITE: 344 MB/Sec (Tricky)


Indeed, configuration 3 shows more writing speed, in tests where caches do not come into play.

RageMem: WRITE64 test:
Interleaved: 3252 MB/Sec
Not Interleaved: 2295 MB/sec

Stream_memspeed: Write test (memset 750 0 - only blocks >= 5MB)
Interleaved: 3363 MB/Sec
Not Interleaved: 2290 MB/sec

Thanks everyone for the contribution.


Edited by AlfredOne on 2024/2/16 9:55:08
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Re: X1000 and interleaved memory controllers
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@AlfredOne
Interesting reading, thanks for sharing results!

It is nice, that interleaving works with PA-Semi CPU.
You are using modules with more ranks, and controller always interleaves the ranks, and in case of use two channels it interleaves also channels.

I think, that rank interleaving is something like: one rank can be accessed and second is refreshed in the same time - i.e. it looks like you not need refreshing cycle.
What is for me interesting, that there are no any additional increase with read operations with dualchannel ( channel interleave ), only with write operations. I thought, that channel interleaving works like: I have two 64-bit channels, which operates like one 128-bit channel...

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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Re: X1000 and interleaved memory controllers
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@geennaam

thanks for explanation. I corrected my understanding of controller interleaving.

But still remains question, why on PA-6T interleaved controllers speeds up write operations and not read operations.

Do you have any idea? One think is that can be caused by used benchmark...

AmigaOS3: Amiga 1200
AmigaOS4: Micro A1-C, AmigaOne XE, Pegasos II, Sam440ep, Sam440ep-flex, AmigaOne X1000
MorphOS: Efika 5200b, Pegasos I, Pegasos II, Powerbook, Mac Mini, iMac, Powermac Quad
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Re: X1000 and interleaved memory controllers
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@sailor

Not sure to be honest. Memory speed is low for any AmigaOne compared to PCs with equivalent DDR technkgy.
It could be related to the fact that the Pa6t has a hardware prefetcher.

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