I tested the following 3 configurations:
1) 1x2GB DIMM on Slot1
CFE relevant output:
SDRAM: ECC off, Non-ECC DIMM used on channel 0.␍␊
[09:30:40:111] DRAM runtime configuration:␍␊
[09:30:40:130] Total memory: 2048MB␍␊
[09:30:40:130] XAUI␍␊
[09:30:40:130] ␍␊
[09:30:40:130] Channel 0:␍␊
[09:30:40:130] 2048MB of RAM, Address Range 0 - 2048MB␍␊
[09:30:40:130] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[09:30:40:130] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[09:30:40:130] High performance mode␍␊
[09:30:40:170] MMC advanced features␍␊
[09:30:40:170] DRAM Rtt: 150 Ohms␍␊
[09:30:40:170] MMC Rtt0: 75 Ohms␍␊
[09:30:40:170] MMC Rtt1: 75 Ohms␍␊
[09:30:40:170] MC & DRAM ODT␍␊
[09:30:40:170] Addr/Cmd 2T Timing␍␊
[09:30:40:170] Ctrl Output Phase wrt CLK: 0␍␊
[09:30:40:170] Addr/Cmd Output Phase wrt CLK: 0␍␊
[09:30:40:170] Rank interleaved␍␊
[09:30:40:170] UDIMM
2) 2x2GB DIMM on Slot1 & Slot2
CFE relevant output:
[09:12:29:334] SDRAM: ECC off, Non-ECC DIMM used on channel 0.␍␊
[09:12:29:338] DRAM runtime configuration:␍␊
[09:12:29:386] Total memory: 4096MB␍␊
[09:12:29:386] XAUI␍␊
[09:12:29:386] ␍␊
[09:12:29:386] Channel 0:␍␊
[09:12:29:386] 4096MB of RAM, Address Range 0 - 6144MB␍␊
[09:12:29:386] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[09:12:29:386] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[09:12:29:386] High performance mode␍␊
[09:12:29:386] MMC advanced features␍␊
[09:12:29:386] DRAM Rtt: 50 Ohms␍␊
[09:12:29:386] MMC Rtt0: 150 Ohms␍␊
[09:12:29:386] MMC Rtt1: 150 Ohms␍␊
[09:12:29:386] MC & DRAM ODT␍␊
[09:12:29:386] Addr/Cmd 2T Timing␍␊
[09:12:29:386] Ctrl Output Phase wrt CLK: 0␍␊
[09:12:29:386] Addr/Cmd Output Phase wrt CLK: 0␍␊
[09:12:29:386] Rank interleaved␍␊
[09:12:29:386] UDIMM
3) 2x2GB DIMM on Slot1 & Slot3
CFE relevant output:
[09:43:48:319] SDRAM: ECC off, Non-ECC DIMM used on channel 0.␍␊
[09:43:48:327] SDRAM: ECC off, Non-ECC DIMM used on channel 1.␍␊
[09:43:48:363] DRAM runtime configuration:␍␊
[09:43:48:363] Total memory: 4096MB␍␊
[09:43:48:363] Channel interleaved ␍␊
[09:43:48:363] XAUI␍␊
[09:43:48:363] ␍␊
[09:43:48:363] Channel 0:␍␊
[09:43:48:363] 2048MB of RAM, Address Range 0 - 6144MB␍␊
[09:43:48:363] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[09:43:48:363] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[09:43:48:363] High performance mode␍␊
[09:43:48:363] MMC advanced features␍␊
[09:43:48:363] DRAM Rtt: 150 Ohms␍␊
[09:43:48:363] MMC Rtt0: 75 Ohms␍␊
[09:43:48:363] MMC Rtt1: 75 Ohms␍␊
[09:43:48:363] MC & DRAM ODT␍␊
[09:43:48:363] Addr/Cmd 2T Timing␍␊
[09:43:48:363] Ctrl Output Phase wrt CLK: 0␍␊
[09:43:48:363] Addr/Cmd Output Phase wrt CLK: 0␍␊
[09:43:48:424] Rank interleaved␍␊
[09:43:48:424] UDIMM␍␊
[09:43:48:424] ␍␊
[09:43:48:424] Channel 1:␍␊
[09:43:48:424] 2048MB of RAM, Address Range 0 - 6144MB␍␊
[09:43:48:424] Memory clock = 400MHz (DDR2-800), tCK = 2500ps, CL = 6␍␊
[09:43:48:424] Low Latency Config Tuned for Fcore = 2000 MHz␍␊
[09:43:48:424] High performance mode␍␊
[09:43:48:424] MMC advanced features␍␊
[09:43:48:424] DRAM Rtt: 150 Ohms␍␊
[09:43:48:424] MMC Rtt0: 75 Ohms␍␊
[09:43:48:424] MMC Rtt1: 75 Ohms␍␊
[09:43:48:424] MC & DRAM ODT␍␊
[09:43:48:424] Addr/Cmd 2T Timing␍␊
[09:43:48:424] Ctrl Output Phase wrt CLK: 0␍␊
[09:43:48:424] Addr/Cmd Output Phase wrt CLK: 0␍␊
[09:43:48:424] Rank interleaved␍␊
[09:43:48:424] UDIMM
RageMem results:
1)
---> RAM <---
READ32: 2822 MB/Sec
READ64: 4049 MB/Sec
WRITE32: 2374 MB/Sec
WRITE64: 2284 MB/Sec
WRITE: 340 MB/Sec (Tricky)
2)
---> RAM <---
READ32: 2837 MB/Sec
READ64: 4077 MB/Sec
WRITE32: 2387 MB/Sec
WRITE64: 2295 MB/Sec
WRITE: 339 MB/Sec (Tricky)
3)
---> RAM <---
READ32: 2827 MB/Sec
READ64: 3961 MB/Sec
WRITE32: 2725 MB/Sec
WRITE64: 3252 MB/Sec
WRITE: 344 MB/Sec (Tricky)
Indeed, configuration 3 shows more writing speed, in tests where caches do not come into play.
RageMem: WRITE64 test:
Interleaved: 3252 MB/Sec
Not Interleaved: 2295 MB/sec
Stream_memspeed: Write test (memset 750 0 - only blocks >= 5MB)
Interleaved: 3363 MB/Sec
Not Interleaved: 2290 MB/sec
Thanks everyone for the contribution.
Edited by AlfredOne on 2024/2/16 9:55:08