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WarpOS/PowerOpenABI vs OS4/ System V.4 ABI problems
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@All
Is anyone by some luck have implmented for vasmppc 4 macroses as in H&P PowerASM prolog/epilog and pushgpr/popgpr ?

I just want to try to port old StormC based powerpc assembler code (which use PowerASM from H&P) to OS4, and with vasmppc_mot it seems all compiles, but only miss those 4 macroses (i had to build vasmppc_mot myself, to have PPC code in motorolla syntax as for PowerASM).

I find out that at least pushgpr/popgpr were implemented in ASM-One rev.483 for compatibility with H&P's PowerASM, but didn't find sources of it.

Those macroses in real-live example used just like this:

Scale a 64x64 texture alpha-channel it

    xdef _GroundAlpha2

_GroundAlpha2
:

    
prolog

    pushgpr r20
-r29

    lwz     r21
,0(r10)
    
lwz     r24,4(r10)
    
lwz     r26,8(r10)
    
lwz     r25,12(r10)


    
addi    r26,r26,1
    andi
.   r23,r0,0

    rlwinm
r10,r7,16,0,31
    mr      r20
,r7
    rlwinm
r20,r20,16,0,31
    rlwinm
r9,r9,16,0,31
    addeo
.  r20,r20,r9
    mr      r7
,r10

    addi    r5
,r5,1
    addi    r4
,r4,-1

_loop
:
    
andi.   r10,r8,$ffc0
    add     r22
,r10,r3

    mr      r20
,r7
        
    mtctr r26       

_loop2
:
    
lhz     r23,1(r4)
    
andi.   r29,r20,$ffff
    lbzx    r29
,r29,r22
    rlwimi  r23
,r29,0,24,31
    lbzx    r29
,r25,r23
    addeo
.  r20,r20,r9
    stbu    r29
,1(r4)

    
bdnz _loop2

    add  r8
,r8,r21
    add  r4
,r4,r24

    addi r5
,r5,-1
    cmpi 0
,0,r5,0
    bne _loop

    popgpr
    epilog



See when we use pushgpr we do have arguments (to point which registers to store), but for popgpr and epilog/prologue we have no arguments.

All information i can find in PowerASM documentation about are this:

Quote:

Nonvolatile registers have to be saved and restored by the function which modifies them.
The 'push' and 'pop' commands can be used for that purpose. Using 'pushgpr', like in our example, you can save as many registers as you want (you can use a register list, known from the 68K command 'movem').
At the command 'popgpr' you don't have to specify the register list, the registers are restored which were saved at the corresponding 'pushgpr'.
Please refer to the documentation of the PowerASM to get a complete description of all 'push' and 'pop' commands.


And there is also powerasm.guide, but it's on german, so what i can translate about are :

prolog

Quote:

Implementation: MACRO

Description: A stack frame is created and a local stack is allocated. All pseudo-mnemonics implicitly associated with the local stack work (e.g. PUSHGPR,PUSHCTR,POPFPR,etc.) may only then be used if a valid stack frame exists.

For a detailed description of this command see chapter Stackframes


epilog

Quote:

Implementation: MACRO

A stack frame created with the PROLOG command is aborted and the return from the function initiated. For a detailed description of this command see chapter "Stackframe".


pushgpr

Quote:

Implementation: Directly in assembler

Several GPR's are pushed onto the stack. The registers are stored from top to bottom, i.e. the register with the lowest number is written to the stack last.

PUSHGPR expects a register list. Individual registers will separated by slashes (/). Areas of registers can be specified as follows: Rm-Rn. Examples of valid ones Register lists:

;
     
r3/r6/r20/r21    includes r3,r6,r20 and r21
     r10
-r13          includes r10,r11,r12,and r13
     r5
/r8-r10/r30    includes r5,r8,r9,r10 and r30
     r3
-r6/r20-r22    includes r3,r4,r5,r6,r20,r21 and r22


The counterpart to PUSHGPR is the POPGPR command

Floating point registers can be pushed onto the stack with the command PUSHFPR get saved.

The PUSHGPR command is exactly the same as the 68K command movem.l RList,-(sp)

Notes: This command may only be used if a valid Stack frame exists (see PROLOG and EPILOG).


Example
       
pushlr           Save link register
       pushctr          
Save Count register
       pushgpr r3
-r8    r3,r4,r5,r6,r7 and r8 rescue
       
...
       
popgpr           restore all 6 GPRs
       popctr           
Restore count register
       poplr            
Restore link register
       blr              
; Exit function




popgpr

Quote:

Implementation: Directly in assembler

Description: Several longwords are loaded from the stack into GPR's. The first longword is loaded into the GPR with the lowest number. A register list can be specified with the POPGPR command. Individual registers are separated by slashes (/). Areas of registers can be specified as follows be: Rm-Rn. Examples of valid register lists:

;
      
r3/r6/r20/r21    includes r3,r6,r20 and r21
      r10
-r13          includes r10,r11,r12,and r13
      r5
/r8-r10/r30    includes r5,r8,r9,r10 and r30
      r3
-r6/r20-r22    includes r3,r4,r5,r6,r20,r21 and r22


If the register list is omitted, the Registers used, saved at the last PUSHGPR. This also works when PUSHGPR and POPGPR be nested. Example:

;
      
pushgpr r6-r9     r6,r7,r8 and r9 are saved
      pushgpr r20
/r21   r20 and r21 are saved
      popgpr            
r20 and r21 are restored
      popgpr            
r6,r7,r8 and r9 will be restored


If to a POPGPR without register list no corresponding match (PUSHGPR) is found, an error message appears generated.

The counterpart to POPGPR is the PUSHGPR" command

Floating point registers can be popped off the stack with the command POPFPR getting charged.

The POPGPR command corresponds to the 68K command movem.l (sp)+,RList

Notes: This command may only be used if a valid Stack frame exists (see PROLOG and EPILOG).

Examples

      
pushlr          Save link register
      pushctr         
Save Count register
      pushgpr r3
-r8   r3,r4,r5,r6,r7 and r8 rescue
      
...
      
popgpr          restore all 6 GPRs
      popctr          
Restore count register
      poplr           
Restore link register
      blr             
; Exit function




So if somebodye can help withthose 4 macroses that will help a lot.

They not need to support slashes, or all the stuff, just pure epilog/prologue and for pushgpr just "pushgpr rx-rx" only.


For pushgpr i assume it just something like this for example for "pushgpr r20-r26":

;
       
stwu    r26,-4(r13)
       
stwu    r25,-4(r13)
       
stwu    r24,-4(r13)
       
stwu    r23,-4(r13)
       
stwu    r22,-4(r13)
       
stwu    r21,-4(r13)
       
stwu    r20,-4(r13)


For "popgpr" i do now know, but i assume it will be something with lwzu..

For Epilog/Prologue it should be something very simple imho, but im not sure how those macroses should be done, so to be 100% the same as it was expected to be in H&P's PowerASM.

Any help much apprecate, thanks!


Edited by kas1e on 2022/4/3 7:39:43
Edited by kas1e on 2022/4/3 7:49:03
Edited by kas1e on 2022/4/8 13:09:18
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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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Lookat here, it's quite simple task replace those macros for GPRS and FPRS regs.
PowerPC assembler is much more robust and simpler than old 68k

IBM docs prolog/epilog

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@flash
Yes that all very easy surely, and i know powerpc docs all over the place.

I asking in hope for those developers working with assembler offten to copy+paste there ready to use 4 macroses in the motorolla format and which will be the same as expected to be on PowerASM from StormC.

Just do not want to spend a day or two for writing and finetuning those simple things, while i am sure some of us know those things very well and can wrote it in a few minutes. But if there will be no other way ...

I can go easy route : take the prolog/epilog used in GCC via disassembly, but i do not know the sizes of prolog/epilog being reserver by default on PowerASM by those macroses. I.e.:

stwu %r1,-16(%r1)    
mflr %r0             # prologue, reserve 16 byte stack frame
stw %r0,20(%r1)      
 
...
 
lwz %r0,20(%r1)      
addi %r1,%r1,16      #  epilogue, restore back
mtlr %r0              
blr


There we reserver 16, but how much it was on PowerASM ? Maybe 16 not enough.

And dunno about pushgprs/popgprs..

Probabaly it worth to just create on original PowerASM some test case which do call those 4 macroses and that all, it will firstly explain how much PowerASM reserve for stack frame and how pushgprs/popgprs is done

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@All
Turns out that at least Epilog and Prolog are happens to be in ppcmacros.i file of WarpOS SDK. Thanks to Frank pointing me out on. He also says that through vasmppc_mot doesn't support the CPU-specific directives, like "equr", "setr", etc.. They exist in vasm's m68k-backend, but not in the PPC-backend.

So we have to rework the prolog/epilog macros yourself by replacing the register names. For exmaple: trash=r0, stack=r1, base=r2.

That the originals we have in WarpOS:

prolog macro
                IFNC 
"","\2"
local setr \2
__LOCAL setr \2
                ENDC
                IFC 
"TOC","\3"
                        
stw base,20(stack)
                
ENDC
                mflr trash
                stw trash
,8(stack)
                
mfcr trash
                stw trash
,4(stack)
                
stw local,-4(stack)
                
subi local,stack,4
                IFC 
"","\1"
__ARGS set 24+4+(__LOCALSIZE)+56
                        stwu stack
,-((__ARGS)-56)(stack)
                ELSEIF
__ARGS set 24+4+(\1)+56
                        stwu stack
,-((__ARGS)-56)(stack)
                
ENDC
                endm

epilog macro
                lwz stack
,0(stack)
                
lwz local,-4(stack)
                
lwz trash,8(stack)
                
mtlr trash
                lwz trash
,4(stack)
                
mtcr trash
                IFC 
"TOC","\1"
                        
lwz base,20(stack)
                
ENDC
                blr
                endm



And that what i have now when replace those stack/trash/local/base things so to be able to compile it with vasmppc_mot:

prolog macro
                IFNC 
"","\2"
local setr \2
__LOCAL setr \2
                ENDC
                IFC 
"TOC","\3"
                        
stw base,20(r1)
                
ENDC
                mflr r0
                stw r0
,8(r1)
                
mfcr r0
                stw r0
,4(r1)
                
stw r13,-4(r1)
                
subi r13,r1,4
                IFC 
"","\1"
__ARGS set 24+4+(__LOCALSIZE)+56
                        stwu r1
,-((__ARGS)-56)(r1)
                ELSEIF
__ARGS set 24+4+(\1)+56
                        stwu r1
,-((__ARGS)-56)(r1)
                
ENDC
                endm                

epilog macro
                lwz r1
,0(r1)
                
lwz r13,-4(r1)
                
lwz r0,8(r1)
                
mtlr r0
                lwz r0
,4(r1)
                
mtcr r0
                IFC 
"TOC","\1"
                        
lwz r2,20(r1)
                
ENDC
                blr
                endm


And while Epilog are ok, for Prolog i have:

Quote:

error 39 in line 16 of "prolog": illegal relocation
called from line 13 of "test.pasm"
> stwu r1,-((__ARGS)-56)(r1)



And i still don't know what to do with pushgprs/popgprs. They implemented in assembler , not via macroses, so hided somewhere.

I currently tried to build HelloWorld on powerasm with epilog/prolog/pushgrps/popgprs and was in hope for some warpos disassembler, but have hard times for. WOS_IRA from os4depot produce mess still, and "wosdb" from aminet just says "can't load binary" (at least on os4). Will try to use wosdb on os3, maybe will be lucky to disassembly and see how at least pushgprs/popgprs looks like from assembler code.

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Re: H&P PowerAsm
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ReWarp uses a form of prolog and epilog.

Also the WarpOS ABI describes r13 as being for local stack and not r1. The original prolog and epilog macros do exactly that (setting up r13).

Edit: nvm. I somehow thought r1 was used but you use r13 correctly.

Edit2: I see I left out the TOC argument in the ReWarp macros, but the sonnet library macros are more complete. You can look there for inspiration.


Edited by Hedeon on 2022/4/4 13:23:11
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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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wosdb uses WarpOS ppc exception handlers that are not(/cannot be ?) implemented as part of the warpos emulation on OS4. It is low-level kernel stuff.

Personally, I use vdappc as a disassembler, but it does not recognize hunks or text.

As for the push/pop stuff, the easiest is just to make a macro that pushes and pulls r14-r31 to r13.

Bloats your code.

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@Hedeon
Checked your macroses from sonet and rewarp : there prolog macro is different for you, its not just "prolog", but you specify size as argument, while in PowerAsm they just have "prolog" with no arguments. And for easy portability i need tge same.. basically that one i post in last post works (seems auto calc necessary size ?), but bring on vasmppc this error:

Quote:

error 39 in line 16 of "prolog": illegal relocation
called from line 13 of "test.pasm"
> stwu r1,-((__ARGS)-56)(r1)


Maybe you know how to fix that ?

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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Well, you say you don't want to use an argument....so remove the __ARGS and replace it with a number (stack size).

However! :

My macros can be used without arguments too. It will then default to 1024 stack size.

So it either takes 0, 1 or 2 arguments. The arguments being TOC (also place r2 on the stack) and stack size.

.macro prolog stacksizedata
    
.if    \data "TOC"
        
stw    r2,20(r1)
    .endif
        
mflr    r0
        stw    r0
,8(r1)
        
mfcr    r0
        stw    r0
,4(r1)
        
stw    r13,-4(r1)
        
subi    r13,r1,4
    
.if    \stacksize ""
        
stwu    r1,-1024(r1)
    .else
        
stwu    r1,-(\stacksize+60)(r1)
    .endif
.
endm


And:

.macro    epilog data
        lwz     r1
,0(r1)
        
lwz     r13,-4(r1)
        
lwz     r0,8(r1)
        
mtlr    r0
        lwz     r0
,4(r1)
        
mtcr    r0
    
.if     (\data "TOC")
        
lwz     r2,20(r1)
        
blr
    
.endif
.
endm


This worked last time I checked. In the past various VASM versions would error on generic arguments like \1 and \2. Haven't tested these in a while.

The 56 or 60 is for room for the volatile registers r3-r12 and some more stuff.

I see in your example lr is saved to 20(r1) but maybe that is SysV ABI which is quite different from the one used in WarpOS.

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@Hedeon
Thanks for you examples. At the moment i end up with those ones which seems works well too (the same which used in powerasm, so i only replae register names):

;
               
IFND __LOCALSIZE
__LOCALSIZE set 1024
                ENDC

prolog macro
                IFNC 
"","\2"
local setr \2
__LOCAL setr \2
                ENDC
                IFC 
"TOC","\3"
                        
stw base,20(r1)
                
ENDC
                mflr r0
                stw r0
,8(r1)
                
mfcr r0
                stw r0
,4(r1)
                
stw r13,-4(r1)
                
subi r13,r1,4
                IFC 
"","\1"
__ARGS set 24+4+(__LOCALSIZE)+56
                        stwu r1
,-((__ARGS)-56)(r1)
                ELSEIF
__ARGS set 24+4+(\1)+56
                        stwu r1
,-((__ARGS)-56)(r1)
                
ENDC
                endm                

epilog macro
                lwz r1
,0(r1)
                
lwz r13,-4(r1)
                
lwz r0,8(r1)
                
mtlr r0
                lwz r0
,4(r1)
                
mtcr r0
                IFC 
"TOC","\1"
                        
lwz r2,20(r1)
                
ENDC
                blr
                endm


Reading VASM tutorial i can see that \1 till \9 are used as arguments too, so even in my case prolog macro can be used with argument as size too.

So as far as i understand if we provide no arguments, so it will be "\1"", then it will allocate: mean 1108 - 56 bytes - 1052. If we provide argument, then it will be taken as number of bytes for alloation, and so will be 24+4+(\1)+56 - 56 , mean 28 as minimum + how muh we allocate.

Next, i tried to just follow the way as you say, so please have a look if it about right or not:

pushgpr:

pushgpr macro

                stwu    r31
,-4(r13)
                
stwu    r30,-4(r13)
                
stwu    r29,-4(r13)
                
stwu    r28,-4(r13)
                
stwu    r27,-4(r13)
                
stwu    r26,-4(r13)
                
stwu    r25,-4(r13)
                
stwu    r24,-4(r13)
                
stwu    r23,-4(r13)
                
stwu    r22,-4(r13)
                
stwu    r21,-4(r13)
                
stwu    r20,-4(r13)
                
stwu    r19,-4(r13)
                
stwu    r18,-4(r13)
                
stwu    r17,-4(r13)
                
stwu    r16,-4(r13)
                
stwu    r15,-4(r13)
                
stwu    r14,-4(r13)
                
                
endm


But for popgprs should it be it all just lwzu by other way arond without anything else ?

I just seems found one of examples of "popgpr" macro, whih was done after "pushgpr r20-r26" and it looks strangely enough, like this:

popgpr:

   
lwz     r20,0(r13)
   
lwzu    r21,4(r13)
   
lwzu    r22,4(r13)
   
lwzu    r6,4(r13)
   
lwzu    r7,4(r13)
   
lwzu    r8,4(r13)
   
lwzu    r9,4(r13)
   
lwzu    r10,4(r13)
   
lwzu    r3,4(r13)
   
lwzu    r4,4(r13)
   
lwzu    r5,4(r13)
   
lwzu    r23,4(r13)
   
lwzu    r24,4(r13)
   
lwzu    r25,4(r13)
   
lwzu    r26,4(r13)
   
addi    r13,r13,4


I didn't get why first one are "lwz", but other ones are "lwzu", also why the order is different (maybe beause originally in StormASM order is different too ? firstly placed one set of registers, then other ones), and that "addi" at then end, seems also need it to have +4 ?


Quote:

I see in your example lr is saved to 20(r1) but maybe that is SysV ABI which is quite different from the one used in WarpOS.


My macroses are straight copy of the WarpOS macroses, just changed those names of registers, so should be "ones used in WarpOS".


EDIT2: btw, such i thing works on PowerASM:

_BlankChunky:
                
la r26,_BlankChunky


But on VASMPPC give that:

Quote:

error: illegal operand types
> la r26,_BlankChunky


Have an idea how it should be for vasmppc ?


Edited by kas1e on 2022/4/4 16:25:16
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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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I think la is indeed used differently on vasm. it is 'la register1, offset(register2)'. You could use that with r2 (TOC) as being register2 for example.

but for the la used in PowerASM you could use something like

.macro    ldaddr registerlabel
    lis    \register
,\label@ha
    addi    \register
,\register,\label@l
.endm

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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I want point also to this fast/simple url about powerpc assembler https://wiibrew.org/wiki/Assembler_Tutorial

Sometimes is faster to replace simple macros instead of resolve them for specific assembler rules not widely supported.

A couple of "lis" and "addi" can be a fast solution to replace "la" macro

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Re: H&P PowerAsm
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@Hedeon
Thanks !

Through as far as i can see PowerASM and VASMPPC_MOT have different syntax in compare with your one. Firstly it didn't have dots at begining, and secondly order reserver, i.e. not " .macro ldaddr register, label", but it's something like "ldaddr macro" (and that all), and then inside of the macros use \1 and \2 for register and label.

At least that how i understand PowerASM/VASMPP_MOT macroses sytax. And if i understand it right, it will be then:

loadaddr macro
    lis    \1
,\2@ha
    addi   \1
,\1,\2@l
endm


as i understan \1 will meanr first arg register, and \2 will mean second arg - string.



@Flash
Quote:

A couple of "lis" and "addi" can be a fast solution to replace "la" macro


Why a couple ? It seems it just one string to replace ? I mean on the link you throw there written:

Quote:

LA - Load Address

Syntax: la rD,d(rA)

This is equivalent to addi rD,rA,d


So if i got it right, then my "la r26,_BlankChunky" is just "addi r26,r26,_BlankChunky" , right ?

EDIT: or, what is better is probabaly this one as Hedeon made in macros (And indeed 2 lines):

_BlankChunky:
        
lis 26,_BlankChunky@ha          # load the address of the label
        
addi r26,26,_BlankChunky@l      # in r26 (2 steps)


Through strange why in the url above it said about one single addi.


Edited by kas1e on 2022/4/4 20:15:48
Edited by kas1e on 2022/4/4 20:16:06
Edited by kas1e on 2022/4/4 20:16:22
Edited by kas1e on 2022/4/4 20:17:33
Edited by kas1e on 2022/4/4 20:25:55
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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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You cannot address a memory location like that as the operands are 16 bits. That is why you need 2 lines to load an address. la is used with a 16 bit offset. So you load for example r2 with a 32 bit address with the macro (let's say DataStart). Then you use
16 bit offsets to this pointer with la as in la r3,_BlankChunky-DataStart(r2)

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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Which is the same as addi r3,r2,_BlankChunky-DataStart

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@Hedeon
The new problem arise.

PowerASM/WarpOS/etc mean PowerOpen-ABI
AmigaOS4 with it's stuff mean V.4-ABI

That all mean, that macroses should be rewritten to be V4 instead of PowerABI, and i fear not only macroses ..

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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About PowerASM you can ask to Sam Jordan http://www.sam-jordan.ch/software.htm

Anyway different ABI lead you to change registers usage.

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@Flash
Quote:

Anyway different ABI lead you to change registers usage.


Seems that difference between PowerAbI and ABI V4, not that big and mostly in the stack layout. So things which works with stack need to be changed (in my case prolog and epilog).

As for registers usage as far as i can see if functions didn't use stack then it may works as it..

Through for example this code crashes for me in some conditions (and in some not) on "lbzx r11,r9,r10":


Draw an icon (alpha-channelled)

External:
r3 opos
r4 tpos
r5 oxpos
r6 ypos
r7 tpos_add
r8 opos_add
r9 alpha

Internal
r10 temp

cmpi 0,0,a,0
ble _skip
; (if a<=0 then goto _skip)

    
xdef DrawIconAlphaAsm

    align 4

DrawIconAlphaAsm
:

    
cmpi    0,0,r5,0
    ble     _end
    cmpi    0
,0,r6,0
    ble     _end
            
    andi
r10,r10,set r10 to 0

_loop1
:
    
mtctr r5


_loop2
:
    
lhz     r11,0(r3)
    
rlwimi  r10,r11,0,16,31
    lbz     r11
,0(r4)
    
addi    r4,r4,1             maybe get rid of this?
    
rlwimi  r10,r11,0,24,31
    lbzx    r11
,r9,r10          CRASH !
    
stb     r11,0(r3)
    
addi    r3,r3,1             maybe get rid of this?
    
bdnz    _loop2


    add  r4
,r4,r7
    add  r3
,r3,r8

    subi r6
,r6,1
    cmpi 0
,0,r6,0
    bgt _loop1


_end
:
    
blr


So maybe this one need ABI v4 adaptation, but at least in terms of registers that what i can see:

r0,r1 and r2 not used there (so no stack pointer, no r2 which different between ABIs)

Registers from r3 to r10 used by arguments, which in both ABIs the same.

The only r11 register mean for PowerABI "volatile, pass static chain if language needs it" and for ABIv4 "volatile, may be used by function linkage", which imho looks ok too, because we port from PowerABIt to V4, not the other way around.

Maybe some of instructions in this code acts differently between ABIs and do change something which make sense ..

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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Educated guess:

r11 is loaded from the address made from r9+r10. r10 is a byte value (seeing rlwinm) and r9 is also not an address (alpha) which gives some undefined address. I am guessing you are getting a DSI error?

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Re: H&P PowerAsm's prolog/epilog and pushgpr/popgpr for vasmppc macros ?
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@Hedeon
There are crashlog, but seems i mess a bit things (or, it just different now), but crash actually on "lbz r11,0(r4)" , but maybe it random. But at least for now 3 times test in a row bring that kind of crash:

Crash log for task "Game_os4.exe"
Generated by GrimReaper 53.19
Crash occured in module Game_os4
.exe at address 0x7ED98120
Type of crash
DSI (Data Storage Interruptexception
Alert number
0x80000003

Register dump
:
GPR (General Purpose Registers):
   
07EDCCA80 61407A50 00000002 5F580CE9 00000023 00000012 0000001A 00000000 
   8
000004EE 5F7AC858 0000CACA 0000CACA 35353333 0000000D 5F574A80 61578D34 
  16
61578BB4 00000000 61578D44 00000000 6140A578 61578DD4 61410000 00000000 
  24
0000C269 00000023 0000BE00 0000001A FFFFFFFF 6144114C 00000000 00000012 


FPR 
(Floating Point RegistersNaN Not a Number):
   
0:             -nan             -nan     -1.07745e-22              0.5 
   4
:                0       4.5036e+15        0.0909089        -0.111111 
   8
:     -2.75573e-07              417             -794              281 
  12
:     4.14104e+204              271     1.43943e+199     -4.71235e+49 
  16
:    -6.88154e-173     6.94802e-236      5.8721e-258     -4.27372e-25 
  20
:     5.64694e-115    -6.69037e-260     7.30915e-220     2.48115e-265 
  24
:    -1.51281e-254    -4.22846e-210     7.82521e-269     1.10112e-226 
  28
:     -1.3764e-260    -2.98016e-264      2.9273e-255     3.57074e+162 

FPSCR 
(Floating Point Status and Control Register): 0x82024000


SPRs 
(Special Purpose Registers):
           
Machine State (msr) : 0x0002F030
                Condition 
(cr) : 0x612B1DC0
      Instruction Pointer 
(ip) : 0x7ED98120
       Xtended Exception 
(xer) : 0x018434C8
                   Count 
(ctr) : 0x00000000
                     Link 
(lr) : 0x00000000
            DSI Status 
(dsisr) : 0x0186395C
            Data Address 
(dar) : 0x00000000



680x0 emulated registers
:
DATA00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 
ADDR
6FFA4000 82CD0900 00000000 00000000 00000000 00000000 00000000 61406D60 
FPU0
:                0                0                0                0 
FPU4
:                0                0                0                0 



Symbol info
:
Instruction pointer 0x7ED98120 belongs to module "Game_os4.exe" (HUNK/Kickstart)

Stack trace:
    
module Game_os4.exe at 0x7ED98120 (section 1 0xFC)
    [
Display.c:1382Game_os4.exe:DrawIconAlpha2()+0xdc (section 1 0xD3B8)
    [
Display.c:4940Game_os4.exe:DrawGraphics()+0x15c (section 1 0x191BC)
    [
Main.c:9602Game_os4.exe:DrawView()+0xee8 (section 1 0x53D44)
    [
Main.c:13820Game_os4.exe:main()+0x21f0 (section 1 0x63B54)
    [/
amiga2/clib2-master/library/stdlib/main.c:134Game_os4.exe:call_main()+0x3c (section 1 0xF2424)
    [/
amiga2/clib2-master/library/stdlib/main.c:412Game_os4.exe:_main()+0x1f8 (section 1 0xF29B0)
    
native kernel module dos.library.kmod+0x0002a490
    native kernel module kernel
+0x0005ea84
    native kernel module kernel
+0x0005eafc

PPC disassembly
:
 
7ed98118a1630000   lhz               r11,0(r3)
 
7ed9811c516a043e   rlwimi            r10,r11,0,16,31
*7ed9812089640000   lbz               r11,0(r4)
 
7ed9812438840001   addi              r4,r4,1
 7ed98128
516a063e   rlwimi            r10,r11,0,24,31

System information
:

CPU 
 Model
Freescale P5020 (E5500 coreV1.2 
 CPU speed
1995 MHz 
 FSB speed
798 MHz 
 Extensions
:  

Machine 
 Machine name
AmigaOne X5000/20 
 Memory
2097152 KB 
 Extensions
bus.pci bus.pcie


Interesting that the same DrawIconAlpha2() asm function is used in the menu and co, and works.

Also, there are my current "abiv4" prolog, epilog, pushgprs/popgprs and loadadr, so to be sure i not make something bad there (as they may be used by other asm functions which may trash something later in stack, but imho should be ok):

prolog macro
        stwu r1
,-1024(r1)    
        
mflr r0             # prologue, reserve 1024 bytes stack frame
        
stw r0,20(r1)      
endm


epilog macro
        lwz r0
,20(r1)
        
mtlr r0 
        addi r1
,r1,1024     #  epilogue, restore back
        
blr                 
endm

pushgpr macro
        stwu    r31
,-4(r1)
        
stwu    r30,-4(r1)
        
stwu    r29,-4(r1)
        
stwu    r28,-4(r1)
        
stwu    r27,-4(r1)
        
stwu    r26,-4(r1)
        
stwu    r25,-4(r1)
        
stwu    r24,-4(r1)
        
stwu    r23,-4(r1)
        
stwu    r22,-4(r1)
        
stwu    r21,-4(r1)
        
stwu    r20,-4(r1)
        
stwu    r19,-4(r1)
        
stwu    r18,-4(r1)
        
stwu    r17,-4(r1)
        
stwu    r16,-4(r1)
        
stwu    r15,-4(r1)
        
stwu    r14,-4(r1)
endm
    
popgpr macro
        lwzu    r14
,0(r1)
        
lwzu    r15,4(r1)
        
lwzu    r16,4(r1)
        
lwzu    r17,4(r1)
        
lwzu    r18,4(r1)
        
lwzu    r19,4(r1)
        
lwzu    r20,4(r1)
        
lwzu    r21,4(r1)
        
lwzu    r22,4(r1)
        
lwzu    r23,4(r1)
        
lwzu    r24,4(r1)
        
lwzu    r25,4(r1)
        
lwzu    r26,4(r1)
        
lwzu    r27,4(r1)
        
lwzu    r28,4(r1)
        
lwzu    r29,4(r1)
        
lwzu    r30,4(r1)
        
lwzu    r31,4(r1)
        
addi    r1,r1,4
endm
                

loadaddr macro
        lis    \1
,\2@ha
        addi   \1
,\1,\2@l        
endm

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Re: WarpOS/PowerOpenABI vs OS4/ System V.4 ABI problems
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@Hedeon

For sake of interest, i just create a simple test case which just do call this DrawIconAlphaAsm, and , via IDA with PPC decompiler made some pseudo-C-byte-code which may help to understand wtf:

DrawIconAlphaAsm.pasm are the same as i show abobe, and main.c just:

#include <stdio.h>

extern void DrawIconAlphaAsmregister unsigned charoposregister unsigned char*, register int oxposregister int yposregister int tpos_addregister int opos_addregister unsigned charalpha ); 

int main()
{

unsigned char *opos
unsigned char *tpos
unsigned charalpha

int yposoxpostpos_addopos_add
    
DrawIconAlphaAsmopostposoxposypostpos_addopos_addalpha ); 
}



Now, after IDA's ppc decompiler to pseudoC code that what we got:

main.c:

int __cdecl main(int argc, const char **argv, const char **envp)
{
  
unsigned __int16 *v4// [sp+8h] [-28h]
  
unsigned __int8 *v5// [sp+Ch] [-24h]
  
int v6// [sp+10h] [-20h]
  
int v7// [sp+14h] [-1Ch]
  
int v8// [sp+18h] [-18h]
  
int v9// [sp+1Ch] [-14h]
  
int v10// [sp+20h] [-10h]

  
DrawIconAlphaAsm(v4v5v6v7v8v9v10);
  return 
0;
}


And our assembler DrawIconAlphaAsm():

unsigned __int16 *__fastcall DrawIconAlphaAsm(unsigned __int16 *resultunsigned __int8 *a2int a3int a4int a5int a6int a7)
{
  
unsigned int v7// r10
  
int v8// ctr
  
unsigned __int8 v9// r11

  
if ( a3 && a4 )
  {
    
v7 0;
    do
    {
      
v8 a3;
      do
      {
        
v9 = *a2++;
        
v7 v9 | (*result v7 0xFFFF0000) & 0xFFFFFF00;
        *(
_BYTE *)result = *(_BYTE *)(a7 v7);
        
result = (unsigned __int16 *)((char *)result 1);
        --
v8;
      }
      while ( 
v8 );
      
a2 += a5;
      
result = (unsigned __int16 *)((char *)result a6);
      --
a4;
    }
    while ( 
a4 );
  }
  return 
result;
}



So.. while it's of course far from the optimal C code, but at least it can be more easy to spot how it expected to work maybe ?

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