I guess that it could be used, if the card uses one of the supported SiI chips (like the SiI3112) and the connection on the card is used similarly like if you had a SATA connection. But I guess this combination is difficult to be found, and if there is something like that worth a try out.
It should be a generic driver, and makes sense because how can you boot from UEFI if it was not.
Its hosted-on git hub in the Linux kernel, we need to make kernel module for ExecSG, and I guess we need support in UBOOT/CFE/OpenFirmware to boot on it.
Even if somebody develops a nvme driver for amigaos, there are some other problems. The P5020/P5040 has PCIe v2.0, which means up to 500MB/s for one lane. The P5020 has 18 lanes, but 8 are unused on the X5000!!! Lane[0-3] are used for PCIe x16 slot.
Lane[4-7] are used with a PCIe-PCIe-switch for the 1 PCIe x4, the 3 PCIe x1 and with a PCIe-PCI-switch for the 2 PCI Slots
Lane[16-17] are used for the 2 SATA-ports
Only if you not use any other PCIe x1 or PCI Card, then you could use a fully connected PCIe x4 Slot, but you need a Riser Card/Cable, because the Slot is mostly blocked by the Headsink of your graphicscard.
The Open Power Notebook design includes M.2 NVME so if there isn't currently support in uboot it will certainly be an item on the checklist for this project. The Notebook also has M.2 slots for Wifi and GSM modems.
With the PCB design now underway I think it's a good time to start working towards driver support for these devices in OS4.
The reason is obvious. The P5020 is targeting embedded network solutions and not generic PC solutions. So the lanes can be configured for a combination of PCIe, SRIO, XAUI, SGMII and SATA interfaces with network applications in mind. You cannot freely assign these interfaces to any serdes lane. You can only choose from 28 different serdes lane/interface configurations.
Table 3-15 in the P5020 reference manual shows the different configurations for the 18 serdes lanes.
When you want to use two SATA controllers then there are only 18 configurations left.
The optimum configuration for PC applications would be SRDS_PRTCL=0x02. This serdes configuration offers: -PCIe1 2.0 x4 -PCIe2 2.0 x4 -PCIe3 2.0 x1 -PCIe4 2.0 x1 -SATA1 2.0 -SATA2 2.0 This is a maximum of 12 out of 18 lanes. (There is also a x8 configuration available but this one is limited to PCIe gen1 speeds. So no improvement in bandwidth at the expense of the x4 slot.)
From design perspective, the X5000 needs 14 lanes. 12 PCIe + 2 SATA. So they needed an external PCIe switch anyways to gain the additional lanes. From performance perspective, it would have been nice that they routed the two unused PCIe lanes to 2 of the PCIe x1 slots directly. But since x1 slots are used for audio cards and ethernet cards, this is no loss. Personally, I wouldn't mind to loose 2 PCIe x1 slots or 1 x1 slot and the two PCI slots. This would have saved the costs of the PCIe switch. But this is now the ultimate P5020 solution for an ATX form factor.
The T2080 has similar limitations. The best configuration for this processor is: -PCIe4 3.0 x4 -PCIe1 2.0 x4 -PCIe2 2.0 x2 -PCIe3 2.0 x2 -SATA1 2.0 -SATA2 2.0 This is 14 out of 16 lanes. PCIe4 supports gen3. This doubles the bandwidth compared to the P5020. But graphics chips, or at least the ones that we can use, barely benefit from higher bandwidth. Tomshardware did a nice test about this in: "The Myths Of Graphics Card Performance: Debunked, Part 2". In this acticle, they compared the framerate of the Radeon R9 290x with benchmark software for PCIe 3.0 x16 (15.75GB/s) all the way down to PCIe 1.0 x8 (2GB/s ; same bandwidth as the X5000). The result was 59.6fps versus 56fps. So almost 8 times more bandwidth resulted in only 6.4% more fps.
The two remaining serdes lanes of the T2080 can be used for SGMII. It might be beneficial to the board layout to use the SGMII interface instead of the RGMII interface.